In the efforts for optimizing and creating new operations in various high-speed microcontroller-based devices, such as portable personal computers (PCs), personal digital assistants (PDAs) and the like, significant attention has been given to the further improvement of memory devices.
Most new microprocessor-based applications are configured for high processing speed through implementation of dynamic random access memory (DRAM) devices, including synchronous dynamic random access memory (SDRAM) devices that can operate at significantly higher clock speeds than conventional memory devices. In particular, SDRAM devices are synchronized with the clock speed in which the microprocessor is optimized, thus enabling the number of instructions that the microprocessor can perform at a given time to be increased.
With reference to FIGS. 1A and 1B, an output buffer 100 as may be implemented within an SDRAM device comprises a pair of predriver circuits 102 and 104 and output driver devices 106. A control logic and pull-up predriver circuit 102 is provided for controlling and driving a pull-up transistor MP0, while a control logic and pull-down predriver circuit 104 is provided for controlling and driving a pull-down transistor MN0. Pull-up/down transistors MP0 and MN0 are further connected to a bondpad 108. Control logic and predriver circuits 102 and 104 can be configured with an internally supplied voltage VCCR (or I/O power supply VCCQ) to drive the gates of pull-up/down transistors MP0 and MN0 to provide an output signal.
An important characteristic in the design and operation of DRAM devices is the slew rate performance of the output buffers within the DRAM devices. The slew rate is the rate from which the output from an electronic circuit or device can be driven from one limit to another over the dynamic range of the electronic circuit or device. For DRAM devices, an ideal slew rate is between approximately 2 to 4 volts/nanosecond. The slew rate of the output signal of the output buffers in DRAM applications can significantly affect various timing specifications, including TAC, TDQSQ, and the like. As a result, it is desirable for the slew rate to be relatively constant for such output buffers.
Unfortunately, the slew rate of the output signal of such output buffers is often varied by the power supply, as well as process and temperature variations within the DRAM device. Of these reasons, changes in the power supply is the biggest impediment to constant slew rate operation. For example, for a change in power supply voltage from 2.3 volts to 2.7 volts, the slew rate of the output signal can vary by approximately 40-50% or more.